A NAND flash memory is known as one of EEPROMs. The NAND flash memory comprises NAND cell units each having a small unit area and including memory cells connected in series. The NAND cell units form a memory cell array. Hence, the NAND flash memory can implement a large storage capacity as compared to a NOR flash memory.
A recent NAND flash memory needs microfabrication of memory cells to further increase the storage capacity. As a manufacturing method for such memory cell microfabrication, a sidewall patterning process has been proposed.
However, the sidewall patterning process generates a difference in dimension between gate electrodes of two adjacent memory cells. This difference in dimension leads to errors in predetermined operations (write, read, and erase) in which voltages are applied to the word lines.
In, for example, a programming operation, a single write pass voltage VPASS is applied to all the word lines of non-write target cells normally. However, the required value of VPASS to be applied to the word lines changes between adjacent memory cells because of the difference in dimension of gate electrodes. Not only the difference in dimension of gate electrodes but also a difference in, for example, channel length, diffusion layer width, impurity concentration, or dimension (space) between adjacent memory cells also changes the required value of VPASS to be applied to the word lines between adjacent memory cells. For this reason, FBC (Failure Bit Count) largely increases in a memory cell connected to a word line to which VPASS of required value is not applied.